查看: 5483|回复: 3

[推荐贴] Agilent SystemVue v2009.08

发表于 2010-10-12 12:49:09 | 显示全部楼层 |阅读模式
Agilent SystemVue v2009.08 | 255Mb
/ u& @. A% P4 r8 y

$ k+ K2 r0 W2 M( V2 H" H
4 g% O: F5 c- _+ q
) p0 E) a4 R/ ?! v. o
5 D5 Z% R% v! b+ O' m* s/ a: ?

) F- j: a- K: g

! p/ U& g+ k6 ]1 i) _* S3 IThe new platform system-level CAD system of Agilent Technologies will allow developers of algorithms and system architects to reduce design time by half.: f* |- u3 B3 M5 W; R7 m+ |9 l1 z: p, `. m
Company Agilent Technologies introduced SystemVue 2009, a new platform CAD (EDA) for the design at the system level (ESL-design). Platform SystemVue 2009 allows to halve the time of designing the physical layer of high-performance communications algorithms and system architecture, as in the field of wireless applications, and for the aerospace and defense industries.
6 R: z4 F5 w/ V, U9 i6 N* ~! F" J  I; f
The new platform SystemVue 2009 than the previous proposals CAD of Agilent for system-level, introducing a new category of design tool for system architects and algorithm developers at the highest level of design communication devices. Platform Company Agilent SystemVue 2009 provides an easy to use environment with advanced technology simulation, with the ability to connect to hardware implementation and testing. This allows you to create prototypes algorithms and architectures for complex systems of communication.
) ^( C, \9 P+ a$ p2 e9 P
) L9 Z8 ~5 p  U% \  F& x, a1 e3 HPlatform SystemVue fills an important gap in the design process between the developers of algorithms and a core group of designers, but also reduces cost of ownership, creating a single process technology at a reasonable price. SystemVue complement existing means of computer-aided design of electronics, general, involved in designing a FPGA, digital signal processors (DSP), application of integrated circuits (ASIC) and analog / RF components.' j- L! S$ B  y- ^3 Y% D: S% p

: b  l. M% b9 n8 lPlatform SystemVue 2009 is ideally suited for system designers of high physical layer protocols, as well as developers of algorithms for developing the physical layer of wireless protocols, eg, 3GPP LTE. In aerospace and defense applications, such as software-defined radio (SDR), satellite communications and radar, also find application platform SystemVue 2009.
& r1 r* d* ?2 L/ M! h

6 {+ P* l0 c8 F/ _. ~  c2 [& d% I0 @5 n
 楼主| 发表于 2010-10-12 12:49:50 | 显示全部楼层

! b3 O6 s6 d1 g$ _) V3 u7 Y1 r. h+ F- s3 u7 ~+ e9 |
Key features of the platform SystemVue 2009 are:  G9 @* `- H3 x- K
( x1 t$ J/ ?+ y. v, Z; h
Advanced Simulation
& @, V; T# \% t2 R+ ]modeling the flow of data - processing of signals with different speeds and frequencies, taking into account the real effects of radio frequency at speeds 10 times higher than general-purpose modeling solutions;% o+ c  [" q7 [- F  Z. D5 E# j- |
extensive set of accurate RF / Analog models allows effective partition of the system into parts;
9 ^# N" R, B; A8 q' x& dHundreds of updated libraries save time when working with functions of communication, signal processing, radio-frequency functions, functions with a fixed-point and compatible with the standards of functions;
! m4 G* k$ u6 c! f' {polymorphism allows you to easily switch between the blocks written in C + +, implemented in the m-code, Verilog / VHDL, or based on a graphical user interface, and easy to work with the ESL-design flows.
) h6 J  |8 P1 b- S7 `/ b# ^" w8 z0 u! f* R* ?+ G
Support for mathematical language- L$ r5 k' k- [6 H7 @
This feature provides compatibility with existing algorithms and methods;
! e6 ?! O+ [' {( \9 A; C& Cthere is also support for development, simulation, debug, connectivity and scripting for hardware TCP / IP.6 K& }! l' w9 R0 u2 ^
# G5 N8 \* S/ W# o
Easy-to-use environment- z1 r4 }& O0 p3 [
environment provides for rapid communication system design with the possibility of easy verification;
4 r: i2 S2 j5 h6 H- |generation of VHDL / Verilog includes support for the rapid manufacture of prototypes FPGA.
6 L4 M1 e& ]' F, P2 P! s& h. n; B2 s- j( D7 z# Y: S3 N9 {
SystemVue is a focused EDA environment for electronic system-level (ESL) design that enables system architects and algorithm developers to innovate the physical layer (PHY) of next-generation wireless and aerospace / defense communications systems.
3 b/ z$ h$ P4 J0 i( `7 O: p5 M. z" |& R. p% ^- H, U0 {; I
SystemVue also provides unique value to RF, DSP, and FPGA / ASIC implementers who rely on signal processing to deliver the full value of their hardware platforms.
* j# c* _! r- [4 v% |
* T& Y- A) k( V8 d1 v; xSystemVue replaces general-purpose digital, analog, and math environments by offering a dedicated platform for ESL design and signal processing realization. SystemVue "speaks RF", cuts PHY development and verification time in half, and connects to your mainstream EDA flow.
2 ^" x, ?& [$ y0 l; _0 A7 r1 b- BReasons to Buy SystemVue! D( o" @6 \( |8 j" T6 u8 K0 d+ @
Innovative, easy Use Model avoids inefficiencies of general-purpose tools
0 C6 V4 E$ `$ K  Z  m  I6 rEnhanced simulation is faster, and accounts for more real world RF effects
: E$ @" R; A& K# w1 \Open, polymorphic modeling environment
* E" ~) K3 e9 c; NAccess to deep Agilent application knowledge of wireless standards and communications PHY models enables you to create & validate system architectures and algorithms quickly." P# h$ V9 T+ Y6 ~: v
' v* z7 Z8 h/ L; i
SystemVue 2009 Features and Benefits
" t' }  K. R, O$ d: M' I& Q+ [3 c* P. p2 F! ]3 s! i8 ~
LTE Library
4 C2 f* K. I& k! uSupports LTE v8.5.0 (Dec 2008) with the latest FDD / TDD / MIMO modes. Supports PUSCH Hopping for v8.5.0.
* Y8 {* @" a) j1 w4 cUpdates the generation of DMRS for PUSCH: n DMRS (1) values can be varied from subframes and are selected from table of TS 36.211 v8.5.0.
0 d: b$ R+ X: ^3 q$ ^& z5 Z) _: ^Supports SRS generation and mapping for v8.5.0.
) B& l8 L% L6 O. N2 e% R0 iSupports PUCCH format shorten 1 for v8.5.0.
7 m6 `, l$ \: u0 h) c, TThe random access preamble format 4 PRACH starts 4832 * Ts before the end of the UpPTS at the UE.7 ~7 b8 x0 A2 D% G2 M6 l9 G
Updates Precoding for large delay CDD for v8.5.0.
  t3 g9 i3 C- D) j0 f! FThe BCH block size is fixed to be 24./ x8 |+ J8 J  d/ S) S1 e

7 e, v- Q& D3 W$ yEnhancement Adds the LTE_BCH_Gen part to generate BCH information bits.
" U$ S( t& d2 a$ qUpdates PDCCH settings and mappings to the CCEs (supporting UE-specific and Common search spaces).
+ X7 x+ C$ ^$ }Updates DCI output bit number for Formats 1B, 1D and 2.
1 i7 C6 U0 u% NAdds four example workspaces for Downlink / Uplink channel coding and decoding.
: ?* x# A4 D: n0 IUpdates the LTE_MIMO_Channel part to support 4x4 MIMO channel.1 h1 t* T* O1 C' k
Supports outputting system configuration information in Simulation Log window for top-level signal sources./ \* X0 k; C. `+ i6 a* w  ~) i/ U
Supports outputting input / output port rates and other useful information in Simulation.7 F; m- c8 _0 o$ o
Log window for the LTE parts with the DisplayPortRates parameter./ z6 J* g9 ~8 ]+ X' ^
1 i3 R: v8 o7 x4 H. Z. u, n# p! x
Date Flow Simulation
$ w7 l* x: ~" cIncreased simulation speed for data flow simulations; especially important for fixed-point and LTE models and simulations.
" W7 k1 [. K, z0 n; uFaster architecture-level verifications against system specification with modulated carriers.
6 M7 H. P& i0 M- O# }5 E! P6 s" TLower memory size for data flow simulations.5 ]7 t+ O, p% U4 _3 G. z/ g$ b
Lower memory usage on long, complex simulations, and especially important for architecture-level simulations of MIMO, BER and fading." N7 k5 c# @- |; R
( H7 K) w2 r+ P( }4 I: ]
Data Flow Information Table
9 a9 @" I5 u! o2 _" hAdded a "Display Data Flow Information" check box in the data flow analysis options tab.9 k- k0 a. T# t8 q
Checking this box will automatically create a table displaying the collected data flow information. Such information is useful for diagnostic and understanding data flow operations.0 L# K, R0 r; V4 Y
( q; S% s% k1 Z! F8 H, ?4 Z
Dynamic Buses
8 ?* b3 _! c1 p3 B& z: ~Enables changes in bus-width during a simulation in response to PHY modes and parameter settings; useful for LTE / WiMAX ? MIMO applications.
; o' e  `' o/ q3 D* U, _
$ V0 p7 o" ~/ U, A; l& ?2 BSupport for Multi-Channel VSA6 O: |" \* W( X
Use SystemVue with Agilent PXB, VSA, MXA, ESG / MXG to integrate difficult emerging 2x2 and 4x4 MIMO testing of both algorithms and hardware.2 D2 f/ e$ y: A9 N
Supports reading up to 4 signals concurrently from a VSA instrument.- m- m+ Y+ |, a; j. N
Supports sending up to 4 signals concurrently to a PXB N5106A instrument.
6 a2 ?  i- ^8 L4 Y9 C* n) DSupports sending up to 4 signals concurrently to VSA 89600 Sink part.
9 L# m, t. W4 }! s6 ~1 t8 ~4 }% x
New 'ReadFile' Part Capabilities! }& _; }$ V! ]+ b
Supports file formats compatible with Agilent Instruments for deeper connectivity to hardware verification.
' K& s1 ]2 C# r8 J+ @2 MReadN6030File - Read files for Agilent N6030A Signal Generator (Arbitrary Waveform Generator).
& W; L* E) j  U/ H- h8 Q% K& QReadN5106AFile - Read files for Agilent N5106A Signal Generator (PXB MIMO Receiver Tester) that the Sink writes.
" w( G8 d6 x$ p" ?9 r( P( ^, hReadSignalStudioFile - Read Agilent Signal Studio waveform format file created by Sink or other Agilent software products such as ADS or Signal Studio software.
& m1 m' p8 B3 }! l. a3 F% Q* a! q. b( I7 ]9 ?0 p5 C! J
Note: Currently without SystemVue's LTE or WiMAX ? license, no waveform files created by Signal Studio software can be read; with SystemVue's LTE or WiMAX license, the corresponding waveform file (ie LTE or WiMAX) created by Signal Studio software can be read. It can read all Agilent Signal Studio waveform format files created by Agilent EESof products including ADS.1 R. f& `- N3 ?6 l5 H
Additional File Read and Write Capabilities9 Y  l- ~0 l" g  N( J( q
Supports file formats compatible with Agilent Instruments for deeper connectivity to hardware verification.
3 U: a9 b1 ~8 L6 X; SReadBaseBandStudioFile - Read BaseBand Studio waveform formatted files created by WriteBaseBandStudioFile Part or by other Agilent software products such as ADS or Agilent BaseBand Studio software.+ _1 @( `: _* J. X' m) h. \
WriteBaseBandStudioFile - Write simulation data into a Agilent Baseband Studio formatted file. Supports writing large files sizes (>> 1GB) for streaming signals to the Agilent ESG Arbitrary Waveform Generator using Agilent Baseband Studio.
 楼主| 发表于 2010-10-12 12:50:14 | 显示全部楼层
C + + Modelbuilder Improved
) Z9 `. t& S6 n' ?; X+ jImprovements result in faster simulations and less memory consumption.
3 U. c) F; m( _0 BSupports: User-defined fixed-point models in ModelBuilder.9 S6 P8 k7 B: X9 m# [3 u) O
Ports - single and multi-ports.6 _* i$ b+ a. g3 D. Q6 L# J
Signal types - float, double, int, complex (float or double), anytype, fixed-point.
* s' e$ J7 W1 C: }Timed signals.
( A% l- Q% _( E5 N9 j: t. mEnumerated model parameter types.
3 o& N3 s) w. AAbility to group and hide / unhide parameters in the UI.9 g5 Z, c$ ^7 X3 f* ]  E; a
Easy re-use of model code within another model.. T, e9 e% l. G* U
Model versioning aligned with a SystemVue release version./ P5 [& m1 G7 s; m1 K- u
Portable model code.5 F6 O, X. O2 b7 L/ r. [: @

" b2 u3 S  t  ~) ^3 q' gSystemVue 2007 APG Model Import
" T# |3 u# m  SEnables owners of previous-generation SystemVue platforms to access some of their models in the new platform.
5 [& B' O7 u% y: v( B8 IVideo: Speeding up RF Modulated Carriers by 1000x
' h! G6 W3 c& OVideo: Importing SV2007 APG files into SV20094 x* n, z" N4 |6 _! j$ |
. z$ @- c- ^6 x- y' {$ z
New and Improved Models
$ Q! e) b+ ?, U, i1 P7 ]/ [. `& i( {
Enable various Wireless and A / D applications. Gold Code: GoldCode supports common Gold codes; including codes specific for GPS applications.
3 x5 u( w5 `6 ?1 r8 B& fAtoD: AtoD supports frequency domain specification of jitter (by specifying phase noise).+ j+ X1 u6 F% k7 ?9 Q9 d( V! |/ `0 d7 ~
Linear Feedback Shift Register (LFSR): LFSR supports access to all internal register states.8 q/ Q- C7 x+ T, h% d9 d1 d
Demodulator: Demodulator supports I / Q gain and phase imbalance, I / Q origin offset, I / Q rotation.
# ]  @3 O) H1 I0 S* A) D
2 l* E5 z2 u) @# j  c& UNew and Improved File I / O Operators
' Z  ?; ~, H- L$ N! lEnables more convenient and efficient file I / O using MathLang. Many file I / O functions added with syntax similar to the MathWorks.
8 i: _4 n* b3 T- D( A! g% s+ A/ x; r' a! P! ^: q% X& M& ]% I# o- b
Random Number Generator Improved% b# b' Q' E6 Y; d# F9 c/ @; ]
Ability to select whether the random seed is held constant or changed for each simulation. A constant seed results in reproducible results for each run of an unchanged simulation, important in algorithmic development.. Y4 k. q' K' i) C3 i6 x

# d. B/ }  Z& Z2 \DSP Filter Tool Improvements- W! Q. `, ?  `
Added Blackman-Haris FIR Window filter type.
" r8 |& T  f$ H% BFaster frequency response and group delay computation.& @1 C0 }$ ?( b1 M* B: H0 b
Faster FIR response computation for large number of coefficients.
! ^% W+ Y& z! T; q5 X9 J6 C8 AImproved filter error trapping.7 c. h) Z: ]$ V, Z

% Y" D" m& x6 c& k- C' ]Improved MathLang Model UI
7 ^; V  x9 x+ \2 ^6 kModel symbol automatically conforms to the number and type of input and output ports defined.$ E  g9 Y7 |2 f3 R/ N

* g8 k  }& H5 r8 SNew Comms Examples2 u7 e! X: q; g% n4 u) H
Zigbee comms examples for signal source and channel model: Signal source based on WPAN 802.15.4 that is simpler and less expensive than Bluetooth; the channel model is UWB 2-10GHz.
- o) M: a  C/ O+ |% w; h9 C3 _+ @5 R' |
2 g6 G0 B1 x% X4 F/ t1 x8 WNew HDL Hardware Implementation Examples8 {9 v5 S) j! I  X

) M$ A7 U+ c& Y( V7 W$ b7 ZNew fixed point examples demonstrating HDL model generation for modulators and other signal processing blocks. Provides new, reconfigurable IP for communications blocks that are Cycle-accurate and Target-neutral.( J1 S$ G) \. a9 N
DSP blocks: CIC Filter, Cordic.
7 U( P) y6 s1 j% W0 Q2 _Modulators: BPSK, QPSK, M-ary PSK, M-ary QAM, M-ary FSK.
; c* d' k! p0 iSources: NCOs (NCO, DDS, Dual NCO)." D# T9 {% }, e7 T% x
Coders: DPSK, DQPSK, Radian shifted n-PSK.' W. [1 ?: L+ p) E  G$ \
- L; m1 b; E2 W1 B- w7 {
New Decision Feedback Equalizer (DFE) Example& l8 t( ?5 g6 x: h% v( I9 {9 ~
DFE provides an adaptive decision feedback equalizer based on the LMS algorithm; useful for signal detection and for correcting signal distortions./ M5 U2 M( A& D+ C% _  s0 i& J. X) E

; ^( }( U# @* C3 x, A- i- I4 yLanguage: English
 楼主| 发表于 2010-10-12 12:50:55 | 显示全部楼层
  1. Download from Hotfile; T- d/ U) v- z% n# s$ b" I
    " F8 V" A) @: X8 x
    * w- _$ v% h; [; b0 l
    ' Z4 j/ E( Y/ k& y
  5. 9 R' R# R! O* N' N. u
  6. Download from ULD* s# A. i* G4 c8 W) [8 U1 M
  7. ~6 D% d, a/ z5 ?$ j3 u7 A- b2 ?
    - f- l- c& e4 _9 x

. @, p+ U& B6 _" S
  [7 e! r7 t  J' ], ?
您需要登录后才可以回帖 登录 | 注册


QQ|小黑屋|无图浏览|手机版|网站地图|虚拟仪器家园 ( 沪ICP备13044638号-3 )

GMT+8, 2019-5-20 04:21 , Processed in 0.028332 second(s), 25 queries , Gzip On, MemCache On.

Powered by Discuz! X3.4

© 2001-2017 Comsenz Inc.

快速回复 返回顶部 返回列表